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| E n n n n PRELIMINARY 5 VOLT FlashFileTM MEMORY 28F008SA (x8) High-Density Symmetrically-Blocked Architecture -- Sixteen 64-Kbyte Blocks Extended Cycling Capability -- 100,000 Block Erase Cycles -- 1.6 Million Block Erase Cycles per Chip Automated Byte Write and Block Erase -- Command User Interface -- Status Register System Performance Enhancements -- RY/BY# Status Output -- Erase Suspend Capability n n n n n n Deep Power-Down Mode -- 0.20 A ICC Typical Very High-Performance Read -- 85 ns Maximum Access Time SRAM-Compatible Write Interface Hardware Data Protection Feature -- Erase/Write Lockout during Power Transitions Industry Standard Packaging -- 40-Lead TSOP, 44-Lead PSOP ETOXTM V Nonvolatile Flash Technology -- 12 V Byte Write/Block Erase The 5 Volt FlashFileTM memory 28F008SA's extended cycling, symmetrically blocked architecture, fast access time, write automation and low power consumption provide a more reliable, lower power, lighter weight and higher performance alternative to traditional rotating disk technology. The 28F008SA brings new capabilities to portable computing. Application and operating system software stored in resident flash memory arrays provide instant-on, rapid eXecute-In-Place (XIP) and protection from obsolescence through in-system software updates. Resident software also extends system battery life and increases reliability by reducing disk drive accesses. For high-density data acquisition applications, the 28F008SA offers a more cost-effective and reliable alternative to SRAM and battery. Traditional high-density embedded applications, such as telecommunications, can take advantage of the 28F008SA's nonvolatility, blocking and minimal system code requirements for flexible firmware and modular software designs. The 28F008SA is offered in 40-lead TSOP and 44-lead PSOP packages. Pin assignments simplify board layout when integrating multiple devices in a flash memory array or subsystem. This device uses an integrated Command User Interface and state machine for simplified block erasure and byte write. The 28F008SA memory map consists of 16 separately erasable 64-Kbyte blocks. Intel(R) 28F008SA employs advanced CMOS circuitry for systems requiring low power consumption and noise immunity. Its 85 ns access time provides superior performance when compared with magnetic storage media. A deep power-down mode lowers power consumption to 1 W typical through VCC, crucial in portable computing, handheld instrumentation and other low-power applications. The RP# power control input also provides absolute data protection during system power-up/down. Manufactured on Intel(R) 0.4 micron ETOX V process technology, the 28F008SA provides the highest levels of quality, reliability and cost-effectiveness. NOTE: This document formerly known as 28F008SA 8-Mbit (1-Mbit x 8) FlashFileTM Memory. December 1998 Order Number: 290429-008 Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F008SA may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 80217-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com COPYRIGHT (c) INTEL CORPORATION 1997, 1998 CG-041493 *Third-party brands and names are the property of their respective owners E 28F008SA CONTENTS PAGE PAGE 8.0 DESIGN CONSIDERATIONS........................ 17 8.1 Three-Line Output Control.......................... 17 8.2 RY/BY# and Byte Write/Block Erase Polling....................................................... 17 8.3 Power Supply Decoupling .......................... 17 8.4 VPP Trace on Printed Circuit Boards .......... 22 8.5 VCC, VPP, RP# Transitions and the Command/Status Registers ...................... 22 8.6 Power Up/Down Protection ........................ 22 8.7 Power Dissipation ...................................... 22 9.0 ELECTRICAL SPECIFICATIONS ................. 23 9.1 Absolute Maximum Ratings ....................... 23 9.2 Operating Conditions ................................. 23 9.3 Capacitance............................................... 23 9.4 DC Characteristics ..................................... 24 9.5 Extended Temperature Operating Conditions................................................. 25 9.6 DC Characteristics--Extended Temperature Operation .................................................. 26 9.7 AC Characteristics--Read-Only Operations ................................................ 29 9.8 AC Characteristics--Read-Only Operations-- Extended Temperature Operation .................................................. 30 9.9 AC Characteristics--Write Operations ....... 33 9.10 Block Erase and Byte Write Performance 34 9.11 AC Characteristics--Write Operations-- Extended Temperature Operation ............. 35 9.12 Block Erase and Byte Write Performance-- Extended Temperature Operation ............. 36 9.13 Alternative CE#-Controlled Writes............ 38 9.14 Alternative CE#-Controlled Writes-- Extended Temperature Operation ............. 40 10.0 ORDERING INFORMATION ....................... 42 11.0 ADDITIONAL INFORMATION..................... 42 1.0 PRODUCT OVERVIEW .................................. 5 2.0 PRINCIPLES OF OPERATION..................... 10 2.1 Command User Interface and Write Automation ............................................... 11 2.2 Data Protection.......................................... 11 3.0 BUS OPERATION ........................................ 11 3.1 Read.......................................................... 11 3.2 Output Disable........................................... 11 3.3 Standby ..................................................... 11 3.4 Deep Power-Down..................................... 12 3.5 Intelligent Identifier Operation .................... 12 3.6 Write .......................................................... 13 4.0 COMMAND DEFINITIONS............................ 13 4.1Read Array Command ................................ 13 4.2 Intelligent Identifier Command ................... 15 4.3 Read Status Register Command ............... 15 4.4 Clear Status Register Command ............... 15 4.5 Erase Setup/Erase Confirm Commands .... 15 4.6 Erase Suspend/Erase Resume Commands15 4.7 Byte Write Setup/Write Commands .......... 16 5.0 EXTENDED BLOCK ERASE/BYTE WRITE CYCLING ..................................................... 16 6.0 AUTOMATED BYTE WRITE......................... 16 7.0 AUTOMATED BLOCK ERASE..................... 16 PRELIMINARY 3 28F008SA E REVISION HISTORY Description Revised from Advanced Information to Preliminary Modified Erase Suspend Flowchart Removed -90 speed bin Integrated -90 characteristics into -85 speed bin Combined VPP Standby current and VPP Read current into one V PP Standby current spec with two test conditions (DC Characteristics table) Lowered VLKO from 2.2 V to 2.0 V. PWD renamed to RP# for JEDEC standardization compatibility. Changed IPPS Standby current spec from 10 A to 15 A in DC Characteristics table. Added Extended Temperature Specs for 28F008SA Added IPPR Spec Corrected IPPS Spec Type Added VOHZ (Output High Voltage--CMOS) Spec Added Byte Write Time Spec Minor changes throughout document. Added reset specifications. All components used prior to the publication date of this datasheet are not affected by the new specification. Only devices used after this date must adhere to this new specification. Removed references to reverse pinout throughout document. Added section numbers. Changed document title from 28F008SA 8-Mbit (1-Mbit x 8) FlashFileTM Memory. Number -002 -004 -005 -006 -007 -008 4 PRELIMINARY E 1.0 28F008SA The status register indicates the status of the WSM and when the WSM successfully completes the desired byte write or block erase operation. The RY/BY# output gives an additional indicator of WSM activity, providing capability for both hardware signal of status (versus software polling) and status masking (interrupt masking for background erase, for example). Status polling using RY/BY# minimizes both CPU overhead and system power consumption. When low, RY/BY# indicates that the WSM is performing a block erase or byte write operation. RY/BY# high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep power-down mode. Maximum access time is 85 ns (tACC) over the commercial temperature range (0 C to +70 C) and over VCC supply voltage range (4.5 V to 5.5 V and 4.75 V to 5.25 V). ICC active current (CMOS Read) is 20 mA typical, 35 mA maximum at 8 MHz. When the CE# and RP# pins are at VCC, the ICC CMOS standby mode is enabled. A deep power-down mode is enabled when the RP# pin is at GND, minimizing power consumption and providing write protection. ICC current in deep power-down is 0.20 A typical. Reset time of 400 ns is required from RP# switching high until outputs are valid to read attempts. Equivalently, the device has a wake time of 1 s from RP# high until writes to the CUI are recognized by the 28F008SA. With RP# at GND, the WSM is reset and the status register is cleared. PRODUCT OVERVIEW The 28F008SA is a high-performance 8-Mbit (8,388,608 bit) memory organized as 1 Mbyte (1,048,576 bytes) of 8 bits each. Sixteen 64-Kbyte (65,536 byte) blocks are included on the 28F008SA. A memory map is shown in Figure 5 of this specification. A block erase operation erases one of the sixteen blocks of memory in typically 1.6 seconds, independent of the remaining blocks. Each block can be independently erased and written 100,000 cycles. Erase suspend mode allows system software to suspend block erase to read data or execute code from any other block of the 28F008SA. The 28F008SA is available in the 40-lead TSOP (Thin Small Outline Package, 1.2 mm thick) and 44-lead PSOP (Plastic Small Outline) packages. Pinouts are shown in Figures 2 and 3 of this specification. The Command User Interface (CUI) serves as the interface between the microprocessor or microcontroller and the internal operation of the 28F008SA. Byte Write and Block Erase Automation allow byte write and block erase operations to be executed using a two-write command sequence to the CUI. The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for byte write and block erase operations, including verifications, thereby unburdening the microprocessor or microcontroller. Writing of memory data is performed in byte increments typically within 9 s--an 80% improvement over current flash memory products. IPP byte write and block erase currents are 10 mA typical, 30 mA maximum. VPP byte write and block erase voltage is 11.4 V to 12.6 V. PRELIMINARY 5 28F008SA E 29042901 Figure 1. Block Diagram 6 PRELIMINARY E Table 1. Pin Descriptions Symbol A0-A19 DQ0-DQ7 Type INPUT INPUT/OUTPUT Name and Function CE# INPUT RP# INPUT 28F008SA ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; outputs data during memory array, status register and Identifier read cycles. The data pins are active high and float to tristate off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders, and sense amplifiers. CE# is active low; CE# high deselects the memory device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode. RP# is active low; RP# high gates normal operation. RP# also locks out block erase or byte write operations when active low, providing data protection during power transitions. RP# active resets internal automation. Exit from deep power-down sets device to readarray mode. OUTPUT ENABLE: Gates the device's outputs through the data buffers during a read cycle. OE# is active low. WRITE ENABLE: Controls writes to the CUI and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. READY/BUSY#: Indicates the status of the internal Write State Machine. When low, it indicates that the WSM is performing a block erase or byte write operation. RY/BY# high indicates that the WSM is ready for new commands, block erase is suspended or the device is in deep power-down mode. RY/BY# is always active and does NOT float to tri-state off when the chip is deselected or data outputs are disabled. BLOCK ERASE/BYTE WRITE POWER SUPPLY for erasing blocks of the array or writing bytes of each block. NOTE: With VPP < VPPLMAX, memory contents cannot be altered. OE# WE# INPUT INPUT RY/BY# OUTPUT VPP VCC GND DEVICE POWER SUPPLY (5 V 10%, 5 V 5%) GROUND PRELIMINARY 7 28F008SA E 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TOP VIEW E28F008SA 40-Lead TSOP 10 mm x 20 mm 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC GND GND DQ3 DQ2 DQ1 DQ0 A0 A1 A2 A3 0429_02 A19 A18 A17 A16 A15 A14 A13 A12 CE# VCC VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 Figure 2. TSOP Lead Configurations VPP RP# A11 A10 A9 A8 A7 A6 A5 A4 NC NC A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 PA28F008SA 40-Lead PSOP 0.525" X 1.110" TOP VIEW 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 VCC CE# A12 A13 A14 A15 A16 A17 A18 A19 NC NC NC NC WE# OE# RY/BY# DQ7 DQ6 DQ5 DQ4 VCC 0429_03 Figure 3. PSOP Lead Configuration 8 PRELIMINARY E 28F008SA 29042905 Figure 4. 28F008SA Array Interface to Intel386SL Microprocessor Superset through PI Bus (Including RY/BY# Masking and Selective Power-Down), for DRAM Backup during System SUSPEND, Resident O/S and Applications and Motherboard Solid-State Disk. PRELIMINARY 9 28F008SA 2.0 PRINCIPLES OF OPERATION FFFFF F0000 EFFFF E0000 DFFFF D0000 CFFFF C0000 BFFFF E 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block B0000 AFFFF A0000 9FFFF 90000 8FFFF 80000 7FFFF 70000 6FFFF 60000 5FFFF 50000 4FFFF 40000 3FFFF 30000 2FFFF 20000 1FFFF 10000 0FFFF 64-Kbyte Block 00000 0429_05 The 28F008SA includes on-chip write automation to manage write and erase functions. The Write State Machine (WSM) allows for 100% TTL-level control inputs, fixed power supplies during block erasure and byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up, or after return from deep power-down mode (see Bus Operations), the 28F008SA functions as a read-only memory. Manipulation of external memory-control pins allow array read, standby and output disable operations. Both status register and intelligent identifiers can also be accessed through the CUI when VPP = VPPL. This same subset of operations is also available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables successful block erasure and byte writing of the device. All functions associated with altering memory contents--byte write, block erase, status and intelligent identifier--are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. CUI contents serve as input to the WSM, which controls the block erase and byte write circuitry. Write cycles also internally latch addresses and data needed for byte write or block erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output byte write and block erase status for verification. Interface software to initiate and poll progress of internal byte write and block erase can be stored in any of the 28F008SA blocks. This code is copied to, and executed from, system RAM during actual flash memory update. After successful completion of byte write and/or block erase, code/data reads from the 28F008SA are again possible via the Read Array command. Erase suspend/resume capability allows system software to suspend block erase to read data and execute code from any other block. 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block 64-Kbyte Block Figure 5. Memory Map 10 PRELIMINARY E 2.1 2.2 28F008SA Command User Interface and Write Automation 3.1 Read An on-chip state machine controls block erase and byte write, freeing the system processor for other tasks. After receiving the Erase Setup and Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the status register and RY/BY# output. Byte write is similarly controlled, after destination address and expected data are supplied. The program and erase algorithms of past Intel(R) Flash memories are now regulated by the state machine, including pulse repetition where required and internal verification and margining of data. The 28F008SA has three read modes. The memory can be read from any of its blocks, and information can be read from the intelligent identifier or status register. VPP can be at either VPPL or VPPH. The first task is to write the appropriate read mode command to the CUI (array, intelligent identifier, or status register). The 28F008SA automatically resets to read array mode upon initial device powerup or after exit from deep power-down. The 28F008SA has four control pins, two of which must be logically active to obtain data at the outputs. Chip Enable (CE#) is the device selection control, and when active enables the selected memory device. Output Enable (OE#) is the data input/output (DQ0-DQ7) direction control, and when active drives data from the selected memory onto the I/O bus. RP# and WE# must also be at VIH. Figure 13 illustrates read bus cycle waveforms. Data Protection Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory byte writes/block erases are required) or hardwired to VPPH. When VPP = VPPL, memory contents cannot be altered. The 28F008SA CUI architecture provides protection from unwanted byte write or block erase operations even when high voltage is applied to VPP. Additionally, all functions are disabled whenever VCC is below the write lockout voltage VLKO, or when RP# is at VIL. The 28F008SA accommodates either design practice and encourages optimization of the processormemory interface. The two-step byte write/block erase CUI write sequence provides additional software write protection. 3.2 Output Disable With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ7) are placed in a high-impedance state. 3.3 Standby 3.0 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. CE# at a logic-high level (VIH) places the 28F008SA in standby mode. Standby operation disables much of the 28F008SA's circuitry and substantially reduces device power consumption. The outputs (DQ0-DQ7) are placed in a highimpedance state independent of the status of OE#. If the 28F008SA is deselected during block erase or byte write, the device will continue functioning and consuming normal active power until the operation completes. PRELIMINARY 11 28F008SA E Table 2. Bus Operations Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 1, 2 1, 2 RP# VIH VIH VIH VIL VIH VIH CE# VIL VIL VIH X VIL VIL OE# VIL VIH X X VIL VIL WE# VIH VIH X X VIH VIH A0 X X X X VIL VIH VPP X X X X X X DQ0-7 DOUT High Z High Z High Z 89H A2H RY/BY# X X X VOH VOH VOH 1,2,3,4,5 VIH VIL VIH VIL X X DIN X Mode Read Output Disable Standby Deep PowerDown Intelligent Identifier (Mfr) Intelligent Identifier (Device) Write NOTES: 1. Refer to DC Characteristics. When VPP = VPPL, memory contents can be read but not written or erased. 2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. See DC Characteristics for VPPL and VPPH voltages. 3. RY/BY# is VOL when the Write State Machine is executing internal block erase or byte write algorithms. It is V when the OH WSM is not busy, in erase suspend mode or deep power-down mode. 4. Command writes involving block erase or byte write are only successfully executed when VPP = VPPH. 5. Refer to Table 3 for valid DIN during a write operation. 3.4 Deep Power-Down The 28F008SA offers a deep power-down feature, entered when RP# is at VIL. Current draw through VCC is 0.20 A typical in deep power-down mode, with current draw through VPP typically 0.1 A. During read modes, RP#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. The 28F008SA requires time tPHQV (see AC Characteristics-Read-Only Operations) after return from power-down until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The CUI is reset to Read Array, and the upper 5 bits of the status register are cleared to value 10000, upon return to normal operation. During block erase, program or lock-bit configuration, RP#-low will abort the operation. RY/BY# remains low until the reset operation is complete. Memory contents being altered are no longer valid; the data may be partially erased or written. Time tPHWL is required after RP# goes to logic-high (VIH) before another command can be written. 12 This use of RP# during system reset is important with automated write/erase devices. When the system comes out of reset it expects to read from the flash memory. Automated flash memories provide status information when accessed during write/erase modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization would not occur because the flash memory would be providing the status information instead of array data. Intel's Flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application RP# is controlled by the same RESET# signal that resets the system CPU. 3.5 Intelligent Identifier Operation The intelligent identifier operation outputs the manufacturer code, 89H; and the device code, A2H for the 28F008SA. The system CPU can then automatically match the device with its proper block erase and byte write algorithms. PRELIMINARY E 3.6 28F008SA Refer to AC Write Characteristics and the AC Waveforms for Write Operations, Figure 15, for specific timing parameters. The manufacturer- and device-codes are read via the CUI. Following a write of 90H to the CUI, a read from address location 00000H outputs the manufacturer code (89H). A read from address 00001H outputs the device code (A2H). It is not necessary to have high voltage applied to VPP to read the intelligent identifiers from the CUI. 4.0 COMMAND DEFINITIONS Write Writes to the CUI enable reading of device data and Intelligent Identifiers. They also control inspection and clearing of the status register. Additionally, when VPP = VPPH, the CUI controls block erasure and byte write. The contents of the interface register serve as input to the internal state machine. The CUI itself does not occupy an addressable memory location. The interface register is a latch used to store the command and address and data information needed to execute the command. Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased. The Byte Write Setup command requires both appropriate command data and the address of the location to be written, while the Byte Write command consists of the data to be written and the address of the location to be written. The CUI is written by bringing WE# to a logic-low level (VIL) while CE# is low. Addresses and data are latched on the rising edge of WE#. Standard microprocessor write timings are used. When VPPL is applied to the VPP pin, read operations from the status register, intelligent identifiers, or array blocks are enabled. Placing VPPH on VPP enables successful byte write and block erase operations as well. Device operations are selected by writing specific commands into the CUI. Table 3 defines the 28F008SA commands. 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the 28F008SA defaults to read array mode. This operation is also initiated by writing FFH into the CUI. Microprocessor read cycles retrieve array data. The device remains enabled for reads until the CUI contents are altered. Once the internal WSM has started a block erase or byte write operation, the device will not recognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional when VPP = VPPL or VPPH. PRELIMINARY 13 28F008SA E Table 3. Command Definitions Bus Cycles Req'd Notes First Bus Cycle Oper(1) Addr (2) X X X X BA X WA WA Data(3) FFH 90H 70H 50H 20H B0H 40H 10H Write Write Write Write BA X WA WA D0H D0H WD WD Read Read IA X IID SRD Second Bus Cycle Oper(1) Addr (2) Data(3) 1 3 2 1 2 2 2 2 5 5 4 Write Write Write Write Write Write Write Write Command Read Array/Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup/Erase Confirm Erase Suspend/Erase Resume Byte Write Setup/Write Alternate Byte Write Setup/Write NOTES: 1. Bus operations are defined in Table 2. 2. IA = Identifier Address: 00H for manufacturer code, 01H for device code. BA = Address within the block being erased. WA = Address of memory location to be written. 3. SRD = Data read from status register. See Table 4 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of WE#. IID = Data read from Intelligent Identifiers. 4. Following the Intelligent Identifier command, two read operations access manufacture and device codes. 5. Either 40H or 10H are recognized by the WSM as the Byte Write Setup command. 6. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 14 PRELIMINARY E 4.2 4.3 28F008SA Intelligent Identifier Command 4.5 Erase Setup/Erase Confirm Commands The 28F008SA contains an intelligent identifier operation, initiated by writing 90H into the CUI. Following the command write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of A2H. To terminate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the Intelligent Identifier command is functional when VPP = VPPL or VPPH. Read Status Register Command The 28F008SA contains a status register which may be read to determine when a byte write or block erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status Register command (70H) to the CUI. After writing this command, all subsequent read operations output data from the status register, until another valid command is written to the CUI. The contents of the status register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. OE# or CE# must be toggled to VIH before further reads to update the status register latch. The Read Status Register command functions when VPP = VPPL or VPPH. Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the CUI, followed by the Erase Confirm command (D0H). These commands require both appropriate sequencing and an address within the block to be erased to FFH. Block preconditioning, erase and verify are all handled internally by the WSM, invisible to the system. After the two-command erase sequence is written to it, the 28F008SA automatically outputs status register data when read (see Figure 6; Automated Block Erase Flowchart). The CPU can detect the completion of the erase event by analyzing the output of the RY/BY# pin, or the WSM status bit of the status register. When erase is completed, the erase status bit should be checked. If erase error is detected, the status register should be cleared. The CUI remains in read status register mode until further commands are issued to it. This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, reliable block erasure can only occur when VPP = VPPH. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while VPP = VPPL, the VPP status bit will be set to "1." Erase attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. 4.4 Clear Status Register Command 4.6 The erase status and byte write status bits are set to "1"s by the Write State Machine and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 4). By allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively writing several bytes or erasing multiple blocks in sequence). The status register may then be polled to determine if an error occurred during that sequence. This adds flexibility to the way the device may be used. Additionally, the VPP status bit (SR.3) must be reset by system software before further byte writes or block erases are attempted. To clear the Status Register, the Clear Status Register command (50H) is written to the CUI. The Clear Status Register command is functional when VPP = VPPL or VPPH. Erase Suspend/Erase Resume Commands The Erase Suspend command allows block erase interruption in order to read data from another block of memory. Once the erase process starts, writing the erase suspend command (B0H) to the CUI requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The 28F008SA continues to output status register data when read, after the Erase Suspend command is written to it. Polling the WSM status and erase suspend status bits will determine when the erase operation has been suspended (both will be set to "1"). RY/BY# will also transition to VOH. PRELIMINARY 15 28F008SA At this point, a Read Array command can be written to the CUI to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase process. The erase suspend status and WSM status bits of the status register will be automatically cleared and RY/BY# will return to VOL. After the Erase Resume command is written to it, the 28F008SA automatically outputs status register data when read (see Figure 7; Erase Suspend/Resume Flowchart). VPP must remain at VPPH while the 28F008SA is in Erase Suspend. tunneling electric field combine to greatly reduce oxide stress and the probability of failure. A 20Mbyte solid-state drive using an array of 28F008SAs has a MTBF (Mean Time Between Failure) of 33.3 million hours1, over 600 times more reliable than equivalent rotating disk technology. E 6.0 AUTOMATED BYTE WRITE 4.7 Byte Write Setup/Write Commands (40H or 10H) Byte write is executed by a two-command sequence. The Byte Write Setup command (40H or 10H) is written to the CUI, followed by a second write specifying the address and data (latched on the rising edge of WE#) to be written. The WSM then takes over, controlling the byte write and write verify algorithms internally. After the two-command byte write sequence is written to it, the 28F008SA automatically outputs status register data when read (see Figure 8; Automated Byte Write Flowchart). The CPU can detect the completion of the byte write event by analyzing the output of the RY/BY# pin, or the WSM status bit of the status register. Only the Read Status Register command is valid while byte write is active. When byte write is complete, the byte write status bit should be checked. If byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until further commands are issued to it. If byte write is attempted while VPP = VPPL, the VPP status bit will be set to "1." Byte write attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. The 28F008SA integrates the Quick-Pulse programming algorithm of prior Intel Flash devices on-chip, using the CUI, status register and WSM. On-chip integration dramatically simplifies system software and provides processor interface timings to the CUI and status register. WSM operation, internal verify and VPP high voltage presence are monitored and reported via the RY/BY# output and appropriate status register bits. Figure 8, Automated Byte Write Flowchart, shows a system software flowchart for device byte write. The entire sequence is performed with VPP at VPPH. Byte write abort occurs when RP# transitions to VIL, or VPP drops to VPPL. Although the WSM is halted, byte data is partially written at the location where byte write was aborted. Block erasure, or a repeat of byte write, is required to initialize this data to a known value. 7.0 AUTOMATED BLOCK ERASE As above, the Quick-Erase algorithm of prior Intel Flash devices is now implemented internally, including all preconditioning of block data. WSM operation, erase success and VPP high voltage presence are monitored and reported through RY/BY# and the status register. Additionally, if a command other than Erase Confirm is written to the device following Erase Setup, both the Erase status and Byte Write status bits will be set to "1"s. When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 6, Automated Block Erase Flowchart, shows a system software flowchart for block erase. 5.0 EXTENDED BLOCK ERASE/BYTE WRITE CYCLING 1 Intel has designed extended cycling capability into its ETOX flash memory technologies. The 28F008SA is designed for 100,000 byte write/block erase cycles on each of the sixteen 64-Kbyte blocks. Low electric fields, advanced oxides and minimal oxide area per cell subjected to the 16 Assumptions: 10-Kbyte file written every 10 minutes. (20-Mbyte array)/(10-Kbyte file) = 2,000 file writes before erase required. (2000 files writes/erase) x (100,000 cycles per 28F008SA block) = 200 million file writes. (200 x 106 file writes) x (10 min/write) x (1 hr/60 min) = 33.3 x 106 MTBF. PRELIMINARY E 8.0 8.1 28F008SA Erase typically takes 1.6 seconds per block. The Erase Suspend/Erase Resume command sequence allows suspension of this erase operation to read data from a block other than that in which erase is being performed. A system software flowchart is shown in Figure 7, Erase Suspend/Resume Flowchart. The entire sequence is performed with VPP at VPPH. Abort occurs when RP# transitions to VIL or VPP falls to VPPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. 8.2 RY/BY# and Byte Write/Block Erase Polling RY/BY# is a full CMOS output that provides a hardware method of detecting byte write and block erase completion. It transitions low time tWHRL after a write or erase command sequence is written to the 28F008SA, and returns to VOH when the WSM has finished executing the internal algorithm. RY/BY# can be connected to the interrupt input of the system CPU or controller. It is active at all times, not tri-stated if the 28F008SA CE# or OE# inputs are brought to VIH. RY/BY# is also VOH when the device is in erase suspend or deep power-down modes. DESIGN CONSIDERATIONS Three-Line Output Control 8.3 Power Supply Decoupling The 28F008SA will often be used in large memory arrays. Intel provides three control inputs to accommodate multiple memory connections. Threeline control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE#, while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels (ISB), active current levels (ICC) and transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between each VCC and GND, and between its VPP and GND. These high frequency, low inherentinductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. PRELIMINARY 17 28F008SA E Table 4. Status Register Definitions ESS 6 ES 5 BWS 4 VPPS 3 NOTES: R 2 R 1 R 0 RY/BY# or the Write State Machine status bit must first be checked to determine byte write or block erase completion, before the Byte Write or Erase status bit are checked for success. WSMS 7 R.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = BYTE WRITE STATUS 1 = Error in Byte Write 0 = Successful Byte Write SR.3 = VPP STATUS 1 = VPP Low Detect; Operation Abort 0 = VPP OK If the Byte Write and Erase status bits are set to "1"s during a block erase attempt, an improper command sequence was entered. Attempt the operation again. If VPP low status is detected, the status register must be cleared before another byte write or block erase operation is attempted. The VPP status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the byte write or block erase command sequences have been entered and informs the system if V PP has not been switched on. The VPP status bit is not guaranteed to report accurate feedback between VPPL and VPPH. SR.2-SR.0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the status register. 18 PRELIMINARY E Start Bus Operation Write Write Command Erase Setup Erase 28F008SA Comments Data = 40H (10H) Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Check RY/BY# (VOH = Ready, VOL = Busy) or Read Status Register (Check SR.7 1 = Ready, 0 = Busy Toggle OE# or CE# to Update Status Register) Write 20H, Block Address Write D0H, Block Address No WSM Ready? Yes Full Status Check if Desired Block Erase Completed No Suspend Erase? Erase Suspend Loop Yes Standby/Read Repeat for subsequent bytes. Full status check can be done after each byte, or after a sequence of bytes. Write FFH after the last byte write operation to reset the device to read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) No SR.3 = 0? Yes SR.4, 5 = 1? Yes No SR.5 = 0? Yes Byte Write Successful Block Erase Error VPP Range Error No Standby Bus Operation Optional Read Command Comments CPU may already have read status register data in WSM Ready polling above Check SR.3 1 = VPP Low Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error Standby Command Sequence Error Standby SR.3 must be cleared, if set during a block erase attempt, before further attempts are allowed by the Write State Machine. SR.5 is only cleared by the clear status register command in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 0429_07 Figure 6. Automated Block Erase Flowchart PRELIMINARY 19 28F008SA E Bus Operation Write Command Comments Erase Suspend Data = B0H Read Status Register Data = 70H Check RY/BY# (VOH = Ready, VOL = Busy) or Read Status Register (Check SR.7 1 = Ready, 0 = Busy Toggle OE# or CE# to update Status Register) Check SR.6 1 = Suspended Read Array Data = FFH Read array data from block other than that being erased Erase Resume Data = D0H Write Standby/Read Start Write B0H Write 70H Read Status Register SR.7 = 1? Yes No Standby Write No SR.6 = 1? Yes Write FFH Erase Has Completed Write Read Done Reading? Yes Write D0H No Continue Erase 0429_08 Figure 7. Erase Suspend/Resume Flowchart 20 PRELIMINARY E Start Bus Operation Write Write Command Byte Write Setup Byte Write 28F008SA Comments Data = 40H (10H) Addr = Byte to Be Written Data to Be Wriiten Addr = Byte to Be Written Check RY/BY# (VOH = Ready, VOL = Busy) or Read Status Register (Check SR.7 1 = Ready, 0 = Busy Toggle OE# or CE# to Update Status Register) Write 40H (10H), Byte Address Write Byte Address/Data Standby/Read WSM Ready? Yes Full Status Check if Desired Byte Write Completed No Repeat for subsequent bytes. Full status check can be done after each byte, or after a sequence of bytes. Write FFH after the last byte write operation to reset the device to read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) No SR.3 = 0? Yes SR.4 = 0? Yes Byte Write Successful VPP Range Error No Byte Write Error Bus Operation Optional Read Command Comments CPU may already have read status register data in WSM Ready polling above Check SR.3 1 = VPP Low Detect Check SR.4 1 = Byte Write Error Standby Standby SR.3 must be cleared, if set during a byte write attempt, before further attempts are allowed by the Write State Machine. SR.4 is only cleared by the clear status register command in cases where multiple bytes are written before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 0429_06 Figure 8. Automated Byte Write Flowchart PRELIMINARY 21 28F008SA 8.4 VPP Trace on Printed Circuit Boards 8.6 Power Up/Down Protection E Writing flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for writing and erasing. Use similar trace widths and layout considerations given to the VCC power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. The 28F008SA is designed to offer protection against accidental block erasure or byte writing during power transitions. Upon power-up, the 28F008SA is indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the 28F008SA ensures that the CUI is reset to the read array mode on power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The CUI architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. Finally, the device is disabled until RP# is brought to VIH, regardless of the state of its control inputs. This provides an additional level of memory protection. 8.5 VCC, VPP, RP# Transitions and the Command/Status Registers Byte write and block erase completion are not guaranteed if VPP drops below VPPH. If the VPP status bit of the status register (SR.3) is set to "1," a Clear Status Register command must be issued before further byte write/block erase attempts are allowed by the WSM. Otherwise, the byte write (SR.4) or erase (SR.5) status bits of the status register will be set to "1"s if error is detected. If RP# transitions to VIL during byte write and block erase, RY/BY# will remain low until the reset operation is complete. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device power-off, or RP# transitions to VIL, clear the status register to initial value 10000 for the upper 5 bits. The CUI latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state upon powerup, after exit from deep power-down or after VCC transitions below VLKO, is read array mode. After byte write or block erase is complete, even after VPP transitions down to VPPL, the CUI must be reset to read array mode via the Read Array command if access to the memory array is desired. 8.7 Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases usable battery life, because the 28F008SA does not consume any power to retain code or data when the system is off. In addition, the 28F008SA's deep power-down mode ensures extremely low power dissipation even when system power is applied. For example, portable PCs and other power sensitive applications, using an array of 28F008SAs for solidstate storage, can lower RP# to VIL in standby or sleep modes, producing negligible power consumption. If access to the 28F008SA is again needed, the part can again be read, following the tPHQV and tPHWL wakeup cycles required after RP# is first raised back to VIH. See AC Characteristics-- Read-Only and Write Operations and Figures 13 and 15 for more information. 22 PRELIMINARY E 9.0 9.1 28F008SA NOTICE: This datasheet contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Operating Temperature During Read............................ 0 C to +70 C(1) During Block Erase/Byte Write ... 0 C to +70 C Temperature Under Bias ...............-10 C to +80 C Storage Temperature ..................-65 C to +125 C Voltage on Any Pin (except VCC and VPP) with Respect to GND............ -2.0 V to +7.0 V(2) VPP Program Voltage with Respect to GND during Block Erase/Byte Write ....-2.0 V to +14.0 V(2, 3) VCC Supply Voltage with Respect to GND ..... -2.0 V to +7.0 V(2) Output Short Circuit Current .....................100 mA(4) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC + 0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods <20 ns. 3. Maximum DC voltage on VPP may overshoot to +14.0 V for periods <20 ns. 4. Output shorted for no more than one second. No more than one output shorted at a time. 5. 5% VCC specifications reference the 28F008SA-85 in its High Speed configuration. 10% VCC specifications reference the 28F008SA-85 in its Standard configuration, and the 28F008SA-120. 9.2 Operating Conditions Parameter Operating Temperature VCC Supply Voltage (10%) VCC Supply Voltage (5%) 5 5 Notes Min 0 4.50 4.75 Max 70 5.50 5.25 Unit C V V Symbol TA VCC VCC 9.3 Capacitance(1) Symbol Parameter Input Capacitance Output Capacitance Typ 6 8 Max 8 12 Unit pF pF Condition VIN = 0 V VOUT = 0 V TA = 25 C, f = 1 MHz CIN COUT NOTE: 1. Sampled, not 100% tested. PRELIMINARY 23 28F008SA 9.4 DC Characteristics Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 1, 3 1.0 30 Min Typ Max 1.0 10 2.0 100 1.2 35 Unit A A mA A A mA E Test Condition VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE# = RP# = VIH VCC = VCC Max CE# = RP# = VCC 0.2 V RP# = GND 0.2 V IOUT (RY/BY#) = 0 mA VCC = VCC Max, CE# = GND f = 8 MHz, I OUT = 0 mA CMOS Inputs VCC = VCC Max, CE# = V IL f = 8 MHz, I OUT = 0 mA TTL Inputs Byte Write In Progress Block Erase In Progress Block Erase Suspended CE# = VIH VPP VCC RP# = GND 0.2 V VPP > VCC VPP = VPPH Byte Write in Progress VPP = VPPH Block Erase in Progress VPP = VPPH Block Erase Suspended 1 1 0.20 20 Symbol ILI ILO ICCS ICCD ICCR VCC Deep Power-Down Current VCC Read Current 25 50 mA ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPE IPPES VIL VIH VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Read Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage 1 1 1, 2 1 1 10 10 5 1 0.10 30 30 10 15 5.0 200 mA mA mA A A A mA mA A V V 1 1 1 -0.5 2.0 10 10 90 30 30 200 0.8 VCC + 0.5 24 PRELIMINARY E 9.4 Symbol VOL VOH1 VOH2 VPPL VPPH VLKO 28F008SA DC Characteristics (Continued) Parameter Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) Notes 3 3 2.4 0.85 VCC VCC - 0.4 VPP during Normal Operations VPP during Erase/Write Operations VCC Erase/Write Lock Voltage 4 0.0 11.4 2.0 12.0 6.5 12.6 V V V Min Typ Max 0.45 Unit V V V Test Condition VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -2.5 A VCC = VCC Min IOH = -100 A NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, TA = 25 C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the 28F008SA is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Includes RY/BY#. 4. Block erases/byte writes are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 5. Sampled, not 100% tested. 9.5 Extended Temperature Operating Conditions Symbol Parameter Operating Temperature VCC Supply Voltage (10%) VCC Supply Voltage (5%) 5 5 Notes Min -40 4.50 4.75 Max +85 5.50 5.25 Unit C V V TA VCC VCC PRELIMINARY 25 28F008SA 9.6 DC Characteristics--Extended Temperature Operation Parameter Input Load Current Output Leakage Current VCC Standby Current Notes 1 1 1, 3 1.0 30 Min Typ Max 1.0 10 2.0 100 20 35 Unit A A mA A A mA E Test Condition Symbol ILI ILO ICCS VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE# = RP# = VIH VCC = VCC Max CE# = RP# = VCC 0.2 V RP# = GND 0.2 V IOUT (RY/BY#) = 0 mA VCC = VCC Max, CE# = GND f = 8 MHz, I OUT = 0 mA CMOS Inputs VCC = VCC Max, CE# = V IL f = 8 MHz, I OUT = 0 mA TTL Inputs Byte Write In Progress Block Erase In Progress Block Erase Suspended CE# = VIH VPP VCC RP# = GND 0.2 V VPP > VCC VPP = VPPH Byte Write in Progress VPP = VPPH Block Erase in Progress VPP = VPPH Block Erase Suspended ICCD ICCR VCC Deep Power-Down Current VCC Read Current 1 1 0.20 20 25 50 mA ICCW ICCE ICCES IPPS IPPD IPPR IPPW IPPE IPPES VIL VIH VCC Byte Write Current VCC Block Erase Current VCC Erase Suspend Current VPP Standby Current VPP Deep Power-Down Current VPP Read Current VPP Byte Write Current VPP Block Erase Current VPP Erase Suspend Current Input Low Voltage Input High Voltage 1 1 1, 2 1 1 10 10 5 1 0.10 30 30 10 15 5.0 200 mA mA mA A A A mA mA A V V 1 1 1 -0.5 2.0 10 10 90 30 30 200 0.8 VCC + 0.5 26 PRELIMINARY E 9.6 Symbol VOL VOH1 VOH2 VPPL VPPH VLKO 28F008SA DC Characteristics--Extended Temperature Operation (Continued) Parameter Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) Notes 3 3 2.4 0.85 VCC VCC - 0.4 VPP during Normal Operations VPP during Erase/Write Operations VCC Erase/Write Lock Voltage 4 0.0 11.4 2.0 12.0 6.5 12.6 V V V Min Typ Max 0.45 Unit V V V Test Condition VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = -2.5 mA VCC = VCC Min IOH = -2.5 A VCC = VCC Min IOH = -100 A NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, TA = 25 C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the 28F008SA is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Includes RY/BY#. 4. Block erases/byte writes are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 5. Sampled, not 100% tested. PRELIMINARY 27 28F008SA E 2.0 Input Test Points 0.8 2.0 Output 0.8 3.0 Input 0.0 1.5 Test Points 1.5 Output 2.4 0.45 0245_06 0245_08 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. AC test inputs are driven at 3.0 V for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at 1.5 V. Input rise and fall times (10% to 90%) <10 ns. Figure 9. Testing Input/Output Waveform(1) Figure 11. High Speed AC Testing Input/Output Waveforms(2) 1.3V 1N914 RL = 3.3 k Device Under Test Out CL = 100 pF 0245_07 1.3V 1N914 RL = 3.3 k Device Under Test Out CL = 30 pF 0245_09 NOTE: CL includes Jig Capacitance NOTE: CL includes Jig Capacitance Figure 10. AC Testing Load Circuit(1) Figure 12. High Speed AC Testing Load Circuit(2) NOTES: 1. Testing characteristics for 28F008SA-85 in Standard configuration, and 28F008SA-120. 2. Testing characteristics for 28F008SA-85 in High Speed configuration. 28 PRELIMINARY E 9.7 Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH 28F008SA AC Characteristics--Read-Only Operations(1) Versions VCC 5% VCC 10% Parameter Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output Low Z CE# High to Output High Z OE# to Output Low Z OE# High to Output High Z Output Hold from Addresses, CE# or OE# Change, Whichever is First 2 3 3 0 55 2 Notes Min 85 85 28F008SA-85(4) -- Max -- 28F008SA-85(5) Min 90 90 Max -- 28F008SA-120(5) Min 120 120 Max ns ns Unit 85 400 90 400 120 400 ns ns 40 0 45 0 55 50 ns ns 55 ns 3 3 0 30 0 30 0 30 ns ns 3 0 0 0 ns NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. PRELIMINARY 29 28F008SA 9.8 AC Characteristics--Read-Only Operations(1)-- Extended Temperature Operation Versions Symbol Parameter Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output Low Z CE# High to Output High Z OE# to Output Low Z OE# High to Output High Z Output Hold from Addresses, CE# or OE# Change, Whichever is First 2 3 3 3 3 3 0 0 30 0 55 2 VCC 10% Notes 28F008SA-100(5) Min 100 100 100 400 55 Max E Unit ns ns ns ns ns ns ns ns ns ns tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tACC tCE tPWH tOE tLZ tHZ tOLZ tDF tOH NOTES: 1. See AC Input/Output Reference Waveform for timing measurements. 2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE. 3. Sampled, not 100% tested. 4. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 5. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. 30 PRELIMINARY E 28F008SA 29042913 Figure 13. AC Waveform for Read Operations PRELIMINARY 31 28F008SA E RY/BY# (R) VIH VIL P2 RP# (P) VIH VIL P1 Figure 14. AC Waveform for Reset Operation # P1 Sym tPLPH Parameter RP# Pulse Low Time (If RP# is tied to V CC, this specification is not applicable) RP# Low to Reset during Block Erase, Program, or Lock-Bit Configuration 2, 3 Notes Min 100 Max Unit ns P2 tPLRH 12 s NOTES: 1. These specifications are valid for all product versions (packages and speeds). 2. If RP# is asserted when the WSM is not busy (RY/BY# = "1"), the reset will complete within 100 ns. 3. A reset time, tPHQV, is required from the latter of RY/BY# or RP# going high until outputs are valid. 32 PRELIMINARY E 9.9 Symbol tAVAV tPHWL tWC tPS tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tCS tWP 28F008SA AC Characteristics--Write Operations(1) Versions VCC 5% VCC 10% Parameter Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read tVPH VPP Hold from Valid SRD, RY/BY# High 2, 6 5, 6 5, 6 6 0.3 0 0 2 3 4 2 Notes Min 85 1 28F008SA- 85(7) -- Max -- 28F008SA- 85(8) Min 90 1 Max -- 28F008SA- 120(8) Min 120 1 Max ns s Unit 10 40 100 40 40 5 5 10 30 100 10 40 100 40 40 5 5 10 30 100 10 40 100 40 40 5 5 10 30 100 ns ns ns ns ns ns ns ns ns ns tVPS tAS tDS tDH tAH tCH tWPH tWHQV1 tWHQV2 tWHGL tQVVL 6 0.3 0 0 6 0.3 0 0 s sec s ns PRELIMINARY 33 28F008SA NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics--Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. The on-chip Write State Machine incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0) 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. E Unit 9.10 Block Erase and Byte Write Performance Parameter Notes 28F008SA-85 Typ(1) Max 10 2.1 (Note 3) 28F008SA-120 Typ(1) 1.6 0.6 8 Max 10 2.1 (Note 3) sec sec s Block Erase Time Block Write Time Byte Write Time 2 2 1.6 0.6 8 NOTES: 1. 25 C, 12.0 V VPP. 2. Excludes System-Level Overhead. 3. Contact your Intel representative for information on the maximum byte write specification. 34 PRELIMINARY E 9.11 Symbol tAVAV tPHWL tELWL tWLWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHQV1 tWHQV2 tWHGL tQVVL 28F008SA AC Characteristics--Write Operations(1)-- Extended Temperature Operation Versions Parameter Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High WE# High to RY/BY# Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read tVPH VPP Hold from Valid SRD, RY/BY# High 2, 6 5, 6 5, 6 6 0.3 0 0 2 3 4 2 VCC 10% Notes 28F008SA- 100(8) Min 100 1 10 40 100 40 40 5 5 10 30 100 Max ns s ns ns ns ns ns ns ns ns ns ns s sec s ns Unit tWC tPS tCS tWP tVPS tAS tDS tDH tAH tCH tWPH NOTES: 1. Read timing characteristics during erase and byte write operations are the same as during read-only operations. Refer to AC Characteristics--Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. The on-chip WSM incorporates all byte write and block erase system functions and overhead of standard Intel flash memory, including byte program and verify (byte write) and block precondition, precondition verify, erase and erase verify (block erase). 6. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0) 7. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 8. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. PRELIMINARY 35 28F008SA 9.12 Block Erase and Byte Write Performance-- Extended Temperature Operation Parameter Notes 28F008SA-100 Typ (1) E Unit Max 10 2.1 (Note 3) sec sec s 1.6 0.6 8 Block Erase Time Block Write Time Byte Write Time 2 2 NOTES: 1. 25 C, 12.0 V VPP. 2. Excludes System-Level Overhead. 3. Contact your Intel representative for information on the maximum byte write specification. 36 PRELIMINARY E 28F008SA 29042914 Figure 15. AC Waveform for Write Operations PRELIMINARY 37 28F008SA 9.13 Alternative CE#-Controlled Writes Versions VCC 5% VCC 10% 28F008SA- 85(6) -- Min 85 2 1 Max -- 28F008SA- 85(7) Min 90 1 Max -- E 28F008SA- 120(7) Min 120 1 Max ns s Unit 0 50 100 40 40 5 5 0 25 100 100 0 50 100 40 40 5 5 0 25 100 ns ns ns ns ns ns ns ns ns ns Sym tAVAV tPHEL tWC tPS Parameter Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to RY/BY# Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read tVPH VPP Hold from Valid SRD, RY/BY# High Notes tWLEL tELEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tWS tCP tVPS tAS tDS tDH tAH tWH tEPH 0 50 2 3 4 100 40 40 5 5 0 25 tEHQV1 tEHQV2 tEHGL tQVVL 5 5 6 0.3 0 6 0.3 0 0 6 0.3 0 0 s sec s ns 2, 5 0 38 PRELIMINARY NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where CE# defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0) 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. E 28F008SA PRELIMINARY 39 28F008SA 9.14 Alternative CE#-Controlled Writes-- Extended Temperature Operation Versions Symbol Parameter Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High CE# High to RY/BY# Going Low Duration of Byte Write Operation Duration of Block Erase Operation Write Recovery before Read tVPH VPP Hold from Valid SRD, RY/BY# High 2, 5 5 5 6 0.3 0 0 2 3 4 2 VCC10% Notes 28F008SA-100(7) Min 100 1 0 50 100 40 40 5 5 0 25 100 Max E Unit ns s ns ns ns ns ns ns ns ns ns ns s sec s ns tAVAV tPHEL tWLEL tELEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHQV1 tEHQV2 tEHGL tQVVL tWC tPS tWS tCP tVPS tAS tDS tDH tAH tWH tEPH NOTES: 1. Chip-Enable Controlled Writes: Write operations are driven by the valid combination of CE# and WE#. In systems where CE# defines the write pulsewidth (within a longer WE# timing waveform), all setup, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte write or block erasure. 4. Refer to Table 3 for valid DIN for byte write or block erasure. 5. Byte write and block erase durations are measured to completion (SR.7 = 1, RY/BY# = VOH). VPP should be held at VPPH until determination of byte write/block erase success (SR.3/4/5 = 0) 6. See High Speed AC Input/Output Reference Waveforms and High Speed AC Testing Load Circuits for testing characteristics. 7. See AC Input/Output Reference Waveforms and AC Testing Load Circuits for testing characteristics. 40 PRELIMINARY E 28F008SA 29042915 Figure 16. Alternate AC Waveform for Write Operations PRELIMINARY 41 28F008SA 10.0 ORDERING INFORMATION E Access Speed (ns) 85, 120 Product Line Designator for all Intel(R) Flash products E2 8 F0 0 8 SA- 8 5 Operating Temperature T = Extended Temp Blank = Commercial Temp Package E = Standard 40-Lead TSOP PA = 44=-Lead PSOP TB = 44-Lead PSOP (Ext. Temp.) VALID COMBINATIONS E28F008SA-85 PA28F008SA-85 E28F008SA-120 PA28F008SA-120 TE28F008SA-100 TF28F008SA-100 TB28F008SA-100 11.0 ADDITIONAL INFORMATION Order Number 290597 290598 271296 292180 297183 Note 3 Note 3 Document/Tool 5 Volt FlashFileTM Memory; 28F004S5, 28F008S5, 28F016S5 datasheet 3 Volt FlashFileTM Memory; 28F004S3, 28F008S3, 28F016S3 datasheet 28F008SA 8-Mbit (1-Mbit x 8) Flash Memory SmartDieTM Product Specification AP-625 28F008SC Compatibility with 28F008SA 28F008 SA/SA-L Specification Update AP-359 28F008SA Hardware Interfacing AP-364 28F008SA Automation and Algorithms NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. These documents can be located at the Intel World Wide Web support site, http://www.intel.com/support/flash/memory 42 PRELIMINARY |
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